View MC74AC299-D_4483663.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2001 may, 2001 rev. 5 1 publication order number: mc74ac299/d mc74ac299, mc74act299 8-input universal shift/storage register with common parallel i/o pins the mc74ac299/74act299 is an 8bit universal shift/storage register with 3state outputs. four modes of operation are possible: hold (store), shift left, shift right and load data. the parallel load inputs and flipflop outputs are multiplexed to reduce the total number of package pins. additional outputs are provided for flipflops q 0 , q 7 to allow easy serial cascading. a separate active low master reset is used to reset the register. ? common parallel i/o for reduced pin count ? additional serial inputs and outputs for expansion ? four operating modes: shift left, shift right, load and store ? 3state outputs for busoriented applications ? outputs source/sink 24 ma ? act299 has ttl compatible inputs figure 1. pinout: 20lead packages conductors (top view) 19 20 18 17 16 15 14 2 1 34567 v cc 13 8 12 9 11 10 s 1 ds 7 q 7 i/o 7 i/o 5 i/o 3 i/o 1 cp ds 0 s 0 oe 1 oe 2 i/o 6 i/o 4 i/o 2 i/o 0 q 0 mr gnd pin assignment pin function cp clock pulse input ds 0 serial data input for right shift ds 7 serial data input for left shift s 0 , s 1 mode select inputs mr asynchronous master reset oe 1 , oe 2 3state output enable inputs i/o 0 i/o 7 parallel data inputs or 3state parallel outputs q 0 , q 7 serial outputs http://onsemi.com 1 20 pdip20 n suffix case 738 1 20 1 20 so20 dw suffix case 751 tssop20 dt suffix case 948e device package shipping ordering information mc74ac299n pdip20 18 units/rail mc74act299n pdip20 18 units/rail mc74ac299dw soic20 38 units/rail mc74ac299dwr2 soic20 1000 tape & reel mc74act299dw soic20 38 units/rail mc74act299dwr2 soic20 1000 tape & reel mc74ac299dt tssop20 75 units/rail mc74ac299dtr2 tssop20 2500 tape & reel mc74act299dt tssop20 75 units/rail mc74act299dtr2 tssop20 2500 tape & reel see general marking information in the device marking section on page 9 of this data sheet. device marking information
figure 3. logic diagram dq c d dq c d dq c d dq c d dq c d dq c d dq c d dq c d cp s 0 oe 1 oe 2 i/o 6 i/o 4 i/o 2 i/o 0 q 0 mr s 1 ds 7 q 7 i/o 7 i/o 5 i/o 3 ds 0 i/o 1 cp cp cp cp cp cp cp note: that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. mc74ac299, mc74act299 http://onsemi.com 2 figure 2. logic symbol ds 0 ds 7 q 7 s 0 s 1 cp oe mr q 0 i/o 0 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 7
mc74ac299, mc74act299 http://onsemi.com 3 functional description the mc74ac299/74act299 contains eight edgetriggered dtype flipflops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. the type of operation is determined by s 0 and s 1 , as shown in the truth t able. all flipflop outputs are brought out through 3state buffers to separate i/o pins that also serve as data inputs in the parallel load mode. q 0 and q 7 are also brought out on other pins for expansion in serial shifting of longer words. a low signal on mr overrides the select and cp inputs and resets the flipflops. all other state changes are initiated by the rising edge of the clock. inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of cp, are observed. a high signal on either oe 1 or oe 2 disables the 3 - state buffers and puts the i/o pins in the high impedance state. in this condition the shift, hold, load and reset operations can still occur. the 3state buffers are also disabled by high signals on both s 0 and s 1 in preparation for a parallel load operation. truth table inputs response mr s 1 s 0 cp response l x x x asynchronous reset; q 0 q 7 = low h h h parallel load; i/o n q n h l h shift rights; ds 0 q 0 , q 0 q 1 , etc. h h l shift left; ds 7 q 7 , q 7 q 6 , etc. h l l x hold h = high voltage level l = low voltage level x = immaterial = low-to-high transition maximum ratings* symbol parameter value unit v cc dc supply voltage (referenced to gnd) 0.5 to +7.0 v v in dc input voltage (referenced to gnd) 0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature 65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v v cc @ 3.0 v 150 t r , t f input rise and fall time (note 1) ac devices exce p t schmitt in p uts v cc @ 4.5 v 40 ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v 25 tt f input rise and fall time ( note 2 ) v cc @ 4.5 v 10 ns/v t r , t f in ut rise and fall time (note 2) act devices except schmitt inputs v cc @ 5.5 v 8.0 ns/v t j junction temperature (pdip) 140 c t a operating ambient temperature range 40 25 85 c i oh output current high 24 ma i ol output current low 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac299, mc74act299 http://onsemi.com 4 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v ugee input voltage 4.5 2.25 3.15 3.15 v or v cc 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v au oee input voltage 4.5 2.25 1.35 1.35 v or v cc 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = 50 m a ugee output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 2.56 2.46 v 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 m a au oee output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 0.36 0.44 v 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 24 ma i in maximum input 55 01 10 m a v i =v cc gnd au u leakage current 5.5 0.1 1.0 m a v i = v cc , gnd i ozt maximum 3state current 55 06 60 m a v i (oe) = v il , v ih v i =v cc gnd current 5.5 0.6 6.0 m a v i = v cc , gnd v o = v cc , gnd i old 2minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 m a v in =v cc or gnd a u qu esce supply current 5.5 8.0 80 m a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . ac characteristics (for figures and waveforms see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f ma maximum input 3.3 90 80 mhz 33 f max frequency 5.0 130 105 mh z 33 t plh propagation delay 3.3 8.5 20.5 7.0 22 ns 36 t plh cp to q 0 or q 7 5.0 5.5 14 4.5 15 ns 36 t phl propagation delay 3.3 8.5 21.5 7.0 23 ns 36 t phl cp to q 0 or q 7 5.0 5.5 14.5 5.0 16 ns 36 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac299, mc74act299 http://onsemi.com 5 ac characteristics (for figures and waveforms see section 3 of the on semiconductor fact data book, dl138/d) symbol fig. no. unit 74ac 74ac v cc * (v) parameter symbol fig. no. unit t a = 40 c to +85 c c l = 50 pf t a = +25 c c l = 50 pf v cc * (v) parameter symbol fig. no. unit max min max typ min v cc * (v) parameter t plh propagation delay 3.3 9.0 20.5 7.5 22.5 ns 36 t plh cp to i/o n 5.0 6.0 14.5 5.0 16 ns 36 t phl propagation delay 3.3 10 23 8.5 24.5 ns 36 t phl cp to i/o n 5.0 6.5 16 6.0 17.5 ns 36 t phl propagation delay 3.3 9.0 22.5 7.5 25.0 ns 36 t phl mr to q 0 or q 7 5.0 5.5 15.5 5.0 17.0 ns 36 t phl propagation delay 3.3 9.0 21.5 7.5 24.0 ns 36 t phl mr to i/o n 5.0 5.5 15.0 5.0 16.5 ns 36 t pzh output enable time 3.3 7.0 18 6.0 19.5 ns 37 t pzh oe to i/o n 5.0 4.5 12.5 4.0 13.5 ns 37 t pzl output enable time 3.3 7.0 18 6.0 20.5 ns 38 t pzl oe to i/o n 5.0 5.0 12.5 4.0 14 ns 38 t phz output disable time 3.3 6.5 18.5 5.5 19.5 ns 37 t phz oe to i/o n 5.0 3.5 14 3.0 15 ns 37 t plz output disable time 3.3 5.5 17 4.5 19 ns 38 t plz oe to i/o n 5.0 3.5 12.5 2.0 13.5 ns 38 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 8.0 8.5 ns 39 t s s 0 or s 1 to cp 5.0 5.0 5.5 ns 39 t h hold time, high or low 3.3 0.5 0.5 ns 39 t h s 0 or s 1 to cp 5.0 1.0 1.0 ns 39 t s setup time, high or low 3.3 5.5 6.0 ns 39 t s i/o n to cp 5.0 3.5 4.0 ns 39 t h hold time, high or low 3.3 0 0 ns 39 t h i/o n to cp 5.0 1.0 1.0 ns 39 t s setup time, high or low 3.3 6.5 7.0 ns 36 t s ds 0 or ds 7 to cp 5.0 4.0 4.5 ns 36 t h hold time, high or low 3.3 0 0.5 ns 36 t h ds 0 or ds 7 to cp 5.0 1.0 1.0 ns 36 t cp pulse width low 3.3 4.5 5.0 ns 36 t w cp p u l se wid t h , low 5.0 3.5 3.5 ns 36 t mr pulse width low 3.3 4.5 5.0 ns 39 t w mr p u l se width , low 5.0 3.5 3.5 ns 39 t rec recovery time 3.3 1.5 1.5 ns 39 t rec mr to cp 5.0 1.5 1.5 ns 39 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac299, mc74act299 http://onsemi.com 6 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v ugee input voltage 5.5 1.5 2.0 2.0 v or v cc 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v au oee input voltage 5.5 1.5 0.8 0.8 v or v cc 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = 50 m a ugee output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i oh 24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 m a au oee output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma i in maximum input 55 01 10 m a v i =v cc gnd au u leakage current 5.5 0.1 1.0 m a v i = v cc , gnd i ozt maximum 3-state current 55 06 60 m a v i (oe) = v il , v ih v i =v cc gnd current 5.5 0.6 6.0 m a v i = v cc , gnd v o = v cc , gnd d i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc 2.1 v i old 2minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 m a v in =v cc or gnd a u qu esce supply current 5.5 8.0 80 m a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one output loaded at a time.
mc74ac299, mc74act299 http://onsemi.com 7 ac characteristics (for figures and waveforms see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f max maximum input 50 120 110 mhz 33 f max maximum in ut frequency 5.0 120 110 mh z 33 t plh propagation delay 50 40 12 5 30 14 ns 36 t plh pro agation delay cp to q 0 or q 7 5.0 4.0 12.5 3.0 14 ns 36 t phl propagation delay 50 40 13 5 35 15 ns 36 t phl pro agation delay cp to q 0 or q 7 5.0 4.0 13.5 3.5 15 ns 36 t plh propagation delay 50 45 12 5 45 13 5 ns 36 t plh pro agation delay cp to i/o n 5.0 4.5 12.5 4.5 13.5 ns 36 t phl propagation delay 50 50 15 45 16 5 ns 36 t phl pro agation delay cp to i/o n 5.0 5.0 15 4.5 16.5 ns 36 t phl propagation delay 50 40 15 40 18 ns 36 t phl pro agation delay mr to q 0 or q 7 5.0 4.0 15 4.0 18 ns 36 t phl propagation delay 50 40 14 5 35 17 5 ns 36 t phl pro agation delay mr to i/o n 5.0 4.0 14.5 3.5 17.5 ns 36 t pzh output enable time 50 25 12 15 13 ns 37 t pzh out ut enable time oe to i/o n 5.0 2.5 12 1.5 13 ns 37 t pzl output enable time 50 20 12 15 13 5 ns 38 t pzl out ut enable time oe to i/o n 5.0 2.0 12 1.5 13.5 ns 38 t phz output disable time 50 20 12 5 20 13 5 ns 37 t phz out ut disable time oe to i/o n 5.0 2.0 12.5 2.0 13.5 ns 37 t plz output disable time 50 25 11 5 20 12 5 ns 38 t plz out ut disable time oe to i/o n 5.0 2.5 11.5 2.0 12.5 ns 38 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac299, mc74act299 http://onsemi.com 8 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 50 55 ns 39 t s setu time , high or low s 0 or s 1 to cp 5.0 5.0 5.5 ns 39 t h hold time, high or low 50 10 10 ns 39 t h hold time , high or low s 0 or s 1 to cp 5.0 1.0 1.0 ns 39 t s setup time, high or low 50 40 45 ns 39 t s setu time , high or low i/o n to cp 5.0 4.0 4.5 ns 39 t h hold time, high or low 50 10 10 ns 39 t h hold time , high or low i/o n to cp 5.0 1.0 1.0 ns 39 t s setup time, high or low 50 45 50 ns 36 t s setu time , high or low ds 0 or ds 7 to cp 5.0 4.5 5.0 ns 36 t h hold time, high or low 50 10 10 ns 36 t h hold time , high or low ds 0 or ds 7 to cp 5.0 1.0 1.0 ns 36 t w cp pulse width 50 40 45 ns 39 t w cp pulse width high or low 5.0 4.0 4.5 ns 39 t mr pulse width low 50 35 35 ns 39 t w mr p u l se width , low 5.0 3.5 3.5 ns 39 t rec recovery time 50 15 15 ns 39 t rec recovery time mr to cp 5.0 1.5 1.5 ns 39 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 170 pf v cc = 5.0 v
mc74ac299, mc74act299 http://onsemi.com 9 ac 299 alyw ac299 awlyyww mc74ac299n awlyyww marking diagrams pdip20 so20 tssop20 act 299 alyw act299 awlyyww mc74act299n awlyyww a = assembly location wl, l = wafer lot yy, y = year ww, w = work week
mc74ac299, mc74act299 http://onsemi.com 10 package dimensions pdip20 n suffix 20 pin plastic dip package case 73803 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc so20 dw suffix 20 pin plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc74ac299, mc74act299 http://onsemi.com 11 package dimensions tssop20 dt suffix 20 pin plastic tssop package case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t
mc74ac299, mc74act299 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74ac299/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

▲Up To Search▲

Price & Availability of MC74AC299-D

	To Download MC74AC299-D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .